Espressif ESP32-S31: The First ESP32 with Gigabit Ethernet and Full Wireless Stack — A Deep Dive

The ESP32 family just grew a new flagship. Espressif Systems has quietly introduced the ESP32-S31, a dual-core RISC-V microcontroller that bridges the high-performance compute capabilities of the ESP32-P4 with the mature wireless ecosystem of the ESP32-S3. It is, by any reasonable measure, the most capable wireless ESP32 silicon released to date — and it ships with a feature set that IoT engineers, industrial embedded developers, and Matter protocol implementers have been requesting for years.

What makes the S31 genuinely interesting is not a single killer feature, but the combination: a proper Gigabit Ethernet MAC (a first for any wireless ESP32), full 802.15.4 support covering Zigbee, Thread, and Matter, a 2D Pixel Processing Accelerator, JPEG VPU, 62 GPIOs, and a dual-core RISC-V architecture that finally brings LP/HP core separation to the ESP32 wireless lineup.

Architecture: Dual-Core RISC-V with HP/LP Separation

At the heart of the ESP32-S31 lies a dual-core RISC-V processor subsystem. The high-performance (HP) core is an RV32IMAFCP — a 32-bit RISC-V integer base with Multiply-Divide (M), Atomic (A), Floating-Point (F), Compressed (C), and SIMD/PACK (P) extensions. This is a meaningfully more capable core than the Tensilica LX6 that powered the original ESP32. The floating-point unit and SIMD instructions make it substantially faster for signal processing, image filtering, and any numeric-heavy workload that would have required fixed-point emulation on earlier ESP32 silicon.

The second core is a low-power (LP) RISC-V MCU, architecturally distinct from the HP core and dedicated to background tasks, wake-up handling, and ultra-low-power standby operations. This HP/LP separation mirrors what Espressif implemented in the ESP32-P4, but with the critical addition of wireless connectivity — making the S31 the first ESP32 to combine P4-class dual-core architecture with the wireless capabilities that made the ESP32 name.

From the soc_caps.h header file leaked in the ESP-IDF repository, the CPU capabilities are extensive:

SOC_CPU_CORES_NUM = 2 — confirmed dual-core
SOC_CPU_HAS_FPU = 1 — hardware floating-point unit present
SOC_CPU_HAS_FPU_EXT_ILL_BUG = 1 — notes an EXT_ILL CSR limitation with FLW/FSW instructions
SOC_CPU_HAS_HWLOOP = 1 — hardware loop instructions (zero-overhead loops)
SOC_CPU_HAS_PIE = 1 — PIE (Position Independent Executable) coprocessor assembly support
SOC_SIMD_PREFERRED_DATA_ALIGNMENT = 16 — 16-byte alignment required for optimal SIMD performance
SOC_CPU_BREAKPOINTS_NUM = 4 and SOC_CPU_WATCHPOINTS_NUM = 4 — robust debug support
SOC_CPU_PMP_REGION_GRANULARITY = 128 — Physical Memory Protection with 128-byte granularity
SOC_BRANCH_PREDICTOR_SUPPORTED = 1 — hardware branch prediction

The shared L1 cache between instruction and data (SOC_SHARED_IDCACHE_SUPPORTED = 1) is also notable, as it simplifies cache management for the HP core while maintaining write-back and freeze capabilities.

Memory: 512KB SRAM, 64MB External PSRAM/Flash Support

The internal SRAM budget stands at 512 KB for the HP subsystem, with an additional 32 KB of RTC SRAM available for low-power state retention. This is a meaningful step up from the ESP32-S3’s 512 KB total (no LP-dedicated split), and the architecture matches the ESP32-P4 in raw SRAM capacity.

Espressif has also enabled support for external octal PSRAM and Flash up to 64 MB, accessed through the dedicated SPI memory (SPIMEM) interfaces. From the peripheral address map in esp32s31.peripherals.ld, four SPIMEM controllers are visible at addresses 0x20501000 through 0x20503000, alongside the standard SPIMEM0 at 0x20500000. The MSPI (Multi-SPI) IOMUX at 0x20584000 handles pin multiplexing for these high-speed memory interfaces, and the SOC_MEMSPI_ENCRYPTION_ALIGNMENT = 16 flag confirms that XTS-AES flash encryption is available with a 16-byte alignment restriction.

For applications requiring DMA to/from external memory, the MMU is configured with SOC_MMU_PER_EXT_MEM_TARGET = 1, meaning the MMU is per physical external memory target (separate page tables for flash and PSRAM), and SOC_DMA_CAN_ACCESS_FLASH = 1 enables DMA transfers directly to/from flash — critical for XiP (execute-in-place) scenarios.

Connectivity: Gigabit Ethernet, WiFi, Bluetooth, and 802.15.4

This is where the ESP32-S31 redefines what a “wireless ESP32” can be. For the first time in the ESP32 lineage, Espressif has integrated a Gigabit Ethernet MAC driven by the GMAC peripheral at address 0x20350000 in the memory map. The GMAC sits alongside a dedicated PVT (physical validation test) block at 0x20354000 — commonly used in Ethernet PHYs for cable diagnostics and link quality monitoring.

Wireless connectivity covers all three major protocols:

2.4 GHz WiFi 802.11 b/g/n — the backbone of ESP32’s IoT dominance
Bluetooth 5.0 — classic BR/EDR and Bluetooth Low Energy
802.15.4 — the foundation for Matter, Thread, and Zigbee smart home protocols

The inclusion of 802.15.4 is strategically significant. Matter, the unified smart home standard backed by Amazon, Apple, Google, and Samsung, runs over Thread (based on 802.15.4) or WiFi. The ESP32-S31’s simultaneous support for WiFi, Bluetooth, and 802.15.4 makes it a natural platform for Matter border routers, Thread nodes, and Zigbee coordinators — all from a single silicon vendor with mature ESP-IDF tooling.

Also worth noting: CNNT_SYS_REG at 0x20359000 and CNNT_PAD_CTRL at 0x20588000 are connectivity subsystem registers and pad control registers that likely handle the radio coexistence logic between WiFi, Bluetooth, and 802.15.4 — a non-trivial engineering problem Espressif has solved in previous multi-radio ESP32 chips.

GPIO Expansion: 62 Pins — Most in ESP32 History

The ESP32-S31 breaks the GPIO record for the ESP32 family with 62 general-purpose I/O pins (SOC_GPIO_PIN_COUNT = 62). The GPIO peripheral base address is 0x20583000, with an extended GPIO block at 0x20583E00. The valid GPIO mask is defined as:

SOC_GPIO_VALID_GPIO_MASK = (((1ULL << 62) - 1) & ~(0ULL | BIT29 | BIT41))

This explicitly excludes GPIO29 and GPIO41 — two pins that are likely reserved for internal functions or not bonded in the package. Eight GPIO pins (GPIO0–GPIO7) support deep sleep wakeup, and there is support for independent LP (low-power) IO wakeup sources (SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE = 1).

The RTCIO subsystem covers SOC_RTCIO_PIN_COUNT = 8, and both force-hold and single-IO hold-in-deep-sleep capabilities are implemented — critical for battery-backed applications that need to maintain state across power cycles.

Multimedia Acceleration: PPA GPU and JPEG VPU

For display and vision applications, the ESP32-S31 carries a 2D Pixel Processing Accelerator (PPA) at address 0x20345000 and a JPEG VPU at 0x20344000. These are the same blocks found in the ESP32-P4, suggesting Espressif has unified its high-performance multimedia IP across both chips.

The PPA handles 2D blitting, color space conversion, alpha compositing, and pixel format conversion — operations that would otherwise consume significant HP core cycles. The JPEG VPU provides hardware-accelerated encoding and decoding of JPEG images, which is essential for camera-over-Parallel-CSI applications.

The peripheral map also includes DMA2D at 0x20346000 (a 2D DMA engine for pixel data movement), LCD_CAM at 0x20396000 for the parallel display and camera interface, and ISP (image signal processor) support — all consistent with a chip targeting HMI (human-machine interface) and vision applications.

However, one important distinction from the P4: the ESP32-S31 appears to lack dedicated MIPI-CSI and MIPI-DSI interfaces. CNX Software reports that the S31 has a parallel camera interface instead. This limits raw camera bandwidth compared to the P4 but keeps the package and routing simpler for cost-sensitive designs.

Peripheral Deep Dive from esp32s31.peripherals.ld

The linker definition file provides a complete peripheral address map. Here is a curated breakdown of what the ESP32-S31 brings to the table:

USB 2.0 OTG (High Speed) at 0x20300000 — USB Host and Device modes
PAU (Power Analysis Unit) at 0x20341000 — power profiling
SDMMC at 0x20342000 — SD/MMC card interface
AHB_DMA (0x20343000) and AXI_DMA (0x20348000) — dual DMA architectures
LP_AHB_DMA at 0x20819000 — DMA accessible from the LP core
RMT at 0x20355000 — remote control transceiver (IR, custom protocols)
ASRC at 0x20357000 — asynchronous sample rate converter for audio
4x MCPWM motors at 0x20381000–0x20384000
4x UART HP at 0x2038A000–0x2038D000, plus LP_UART at 0x20810000
2x I2C HP at 0x20385000–0x20386000, plus LP_I2C at 0x20811000
2x SPI (GPSPI2, GPSPI3) plus LP_SPI at 0x20812000
2x I2S at 0x20387000–0x20388000 — audio interfaces
2x LEDC at 0x20392000 and 0x2039C000 — 6 channels total
2x PCNT (pulse counter) at 0x20389000 and 0x2039D000
2x TWAIFD (Two-Wire Automotive Interface) at 0x20394000–0x20395000
UHCI0 at 0x20398000 — Universal Host Controller Interface
SYSTIMER at 0x20399000 — system timer with 2 counters and 3 alarms
CORDIC at 0x2039B000 — trigonometric co-processor
2x GPTimer at 0x20580000–0x20581000 with ETM support
PMU at 0x20704000 — power management unit
EFUSE at 0x20715000 — eFuse with key-purpose field, 3 secure boot key digests
ADC at 0x20815000 with 10 channels (SOC_ADC_MAX_CHANNEL_NUM = 10)
TOUCH_SENS at 0x20816000 — touch sensor array
TSENS at 0x20818000 — temperature sensor

Security: eFuse, Flash Encryption, and Cryptographic Accelerators

The security subsystem of the ESP32-S31 is comprehensive. The EFUSE block at 0x20715000 supports:

SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS = 3 — up to 3 RSA key digests for secure boot verification
SOC_FLASH_ENCRYPTION_XTS_AES — XTS-AES-128/256 flash encryption
eFuse-based key purpose fields for cryptographic key isolation
JTAG disable bits: SOC_EFUSE_DIS_PAD_JTAG = 1, SOC_EFUSE_DIS_USB_JTAG = 1
SOC_EFUSE_DIS_DIRECT_BOOT = 1 — prevents direct boot from flash bypassing secure boot
SOC_EFUSE_DIS_DOWNLOAD_MSPI = 1 — disables MSPI access in download mode
SOC_EFUSE_ECDSA_KEY = 1 — ECDSA key in eFuse

Dedicated cryptographic accelerators are mapped at:

AES at 0x20508000
SHA at 0x20509000 (SHA-1, SHA-256, etc.)
RSA at 0x2050A000
ECC at 0x2050B000 and ECC_EXTENDED_MODES
DS (Digital Signature) at 0x2050C000
HMAC at 0x2050D000
ECDSA at 0x2050E000

The Key Manager at 0x20506000 handles key deployment, with ECDSA key deployment explicitly supported. The KEYMNG block suggests key rotation and secure key storage capabilities.

ESP32-S31 vs ESP32-P4 vs ESP32-S3: Specification Comparison

Feature	ESP32-S31	ESP32-P4	ESP32-S3
CPU Architecture	Dual-core RISC-V (HP + LP)	Dual-core RISC-V (HP + LP)	Single-core or Dual-core Xtensa LX7
HP Core	RV32IMAFCP (FPU + SIMD)	RV32IMAFCP (FPU + SIMD)	Xtensa LX7 (FPU)
LP Core	Yes (RISC-V LP)	Yes (RISC-V LP)	No (ULP only)
Internal SRAM	512 KB + 32 KB RTC	512 KB + 32 KB RTC	512 KB total
External Memory	64 MB Octal PSRAM/Flash	64 MB Octal PSRAM/Flash	Up to 16 MB PSRAM (octal)
GPIO Count	62	43	45
Gigabit Ethernet	Yes (GMAC)	Yes (GMAC)	No
WiFi 802.11 b/g/n	Yes	No	Yes
Bluetooth	Yes (BT 5.0)	No	Yes (BT 5.0)
802.15.4 (Thread/Zigbee/Matter)	Yes	No	No
2D PPA (GPU)	Yes	Yes	No
JPEG VPU	Yes	Yes	No
H.264 VPU	No	Yes	No
Parallel LCD Interface	Yes	Yes	No
Camera Interface	Parallel (no MIPI-CSI)	MIPI-CSI + Parallel	DVP (8-bit)
USB 2.0 OTG	Yes	Yes	USB 1.1 OTG
UART	4 + 1 LP	4	3
I2C	2 + 1 LP	2	2
SPI	2 + 1 LP	4	4
Flash Encryption	XTS-AES-128/256	XTS-AES-128/256	XTS-AES-128
Secure Boot	Yes (3 key digests)	Yes	Yes
Cryptographic Accelerators	AES, SHA, RSA, ECC, HMAC, ECDSA, DS	AES, SHA, RSA, ECC, HMAC, ECDSA, DS	AES, SHA, RSA, ECC, HMAC

The Missing Pieces: What’s Not in the S31

No silicon is without trade-offs, and the ESP32-S31 makes several deliberate omissions compared to its P4 sibling. The absence of an H.264 VPU means hardware-accelerated video encoding is not available — a limitation for streaming camera applications that would otherwise benefit from the parallel camera interface. Similarly, the lack of MIPI-CSI (only parallel) and MIPI-DSI reduces maximum camera and display bandwidth compared to the P4.

There is only one HP core versus two in the ESP32-P4, so multi-threaded compute workloads will need to offload to the LP core or accept single-core throughput limits. The soc_caps.h also reveals numerous TODO entries with ESP32-specific issue tracker IDs (IDF-146xx, IDF-147xx) — the firmware ecosystem is clearly still in active development, which is expected given this appears to be an early-sample chip.

Notably absent from the capability flags: SOC_ULP_SUPPORTED is commented out, as is SOC_LP_CORE_SUPPORTED — yet SOC_PAU_SUPPORTED (Power Analysis Unit) and SOC_PMU_SUPPORTED are defined, along with the LP subsystem registers. The sleep/wake architecture is clearly present but may be in flux for this first silicon spin.

What This Means for the ESP32 Ecosystem

The ESP32-S31 fills a gap that has existed since Espressif introduced the P4. The ESP32-P4 was a high-performance computing platform without wireless — ideal for edge HMI and display applications. The ESP32-S3 had wireless but lacked the compute headroom for demanding multimedia. The S31 merges these paths: it has P4-class RISC-V performance, the same multimedia acceleration blocks, and the full wireless stack including 802.15.4 for Matter.

The 62 GPIO count is immediately practical for industrial IoT applications where expansion cards and parallel buses are common. The four additional UART channels over the S3 (total 4 HP + 1 LP) address a frequent complaint from multi-serial deployments. And Gigabit Ethernet on a wireless MCU eliminates the need for a separate Ethernet PHY + wireless module combination in many gateway designs.

For developers targeting Matter, the combination of WiFi, Bluetooth, and 802.15.4 on a single chip with ESP-IDF’s established Matter SDK makes the ESP32-S31 arguably the most compelling multi-protocol IoT platform Espressif has ever produced — pending full SDK and documentation release.

Source References

CNX Software: ESP32-S31 Announcement Coverage
ESP32 Forum: ESP32-S31 Discussion Thread
ESP-IDF Source: soc_caps.h
ESP-IDF Source: esp32s31.peripherals.ld

All specifications are preliminary and based on leaked ESP-IDF source files. Final production specifications may differ. This analysis reflects the state of publicly available information as of March 2026.

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